The present invention relates to PROM ICs. More specifically, the invention relates to EPROM ICs, EEPROM ICs, etc. of the type in which a margin test on storage states of respective memory cells can be performed under a stricter condition to enable selection of more reliable memory ICs.
Among nonvolatile memories are a mask ROM that is not rewritable and a PROM that is rewritable. The PROM is further classified into an EPROM that is erasable and rewritable and an EEPROM that electrically erasable and rewritable.
In teams of constitution, there are various types of PROMs. A fuse-type PROM, for instance, is rewritable only once. A FAMOS, for instance, can be erased with ultraviolet rays etc. and then data can be rewritten to it by avalanche breakdown. A MNOS, for instance, functions on the tunneling effect and is electrically erasable and rewritable. In a PROM IC, memory cells of one the above types are arranged in a matrix to constitute a memory array.
Referring to FIG. 3, we explain general constitution of the PROM IC.
Symbols 1a, 1b, . . . denote memory cells as mentioned above. As shogun in FIG. 3, the memory cells 1a, 1b, . . . are arranged in a matrix to constitute a memory array 1.
Numerals 2 and 4 denote a column decoder and a row decoder, respectively. In response to an address signal A (character A also represents an address itself), the column decoder 2 selects a column and the row decoder 4 selects a row, to thereby select a memory cell corresponding to the address A among the memory cells 1a, 1b, . . . arranged in a matrix.
Symbols 5a, 5b, . . . denote sense circuits. When a read voltage is supplied from a read voltage applying circuit 3 to the memory cell (selected memory cell) corresponding to the address A that is selected by the decoders 2 and 4 and information is read out from that memory cell, a resulting readout signal is amplified by a sense amplifier of one of the sense circuits 5a, 5b, . . . When a read voltage that is larger than a predetermined threshold level is applied to the memory cell, the corresponding sense amplifier produces an inverted output. Thus, Each of the sense circuits 5a, 5b, . . . produces a binary output.
When receiving a test selection signal T, the read voltage applying circuit 3 switches the read voltage, which is to be applied to the selected memory cell through the column decoder 2, from a standard read voltage S to an external voltage E.
Referring to FIG. 4, we explain a relationship among the read voltage applying circuit 3, a selected memory cell 1c and a corresponding sense circuit 5c (having a sense amplifier SA). The test selection signal T is generated in response to a signal that is externally set to select a test mode.
FIG. 4 shows a state in which the memory cell 1c is selected in the PROM IC of FIG. 3. To provide a clear description, FIG. 4 is simplified such that the memory cells other than the memory cell 1c are omitted and each of the column decoder 2 and the row decoder 3 is drawn simply as a connection line by omitting a transistor for conduction control and other parts. In this example, since the memory cell 1c is constituted of a floating gate type transistor Qc, the read voltage is applied to the gate of the transistor Qc through the column decoder 2.
In the absence of the test selection signal T, that is, in the normal read operation, in which case a transistor Qb is in an off-state, the preset standard read voltage S is supplied, as the read voltage, from the read voltage applying circuit 3 to the gate of the transistor Qc. On the other hand, in the presence of the test signal T, that is, in a performance test such as what is called a margin test, the external voltage E is input, as the read voltage, through a test-dedicated terminal or some other external terminal of the PROM IC, and is then output from the read voltage applying circuit 3 so as to be used to read out the stored information. In this case, the external voltage E is applied to the gate of the transistor Qc of the selected memory cell 1c through the transistor Qb that is in an on-state. In the test operation, the sense circuit 5c, which is connected to the drain of the transistor Qc through the row decoder 4, detects the storage state of the memory cell 1c, i.e., the trap state of electrons or holes in the floating gate of the transistor Qc. This is done by detecting the current drive ability of the transistor Qc when the read voltage is applied to the gate of it.
This is explained more specifically below. The input side of the sense amplifier SA of the sense circuit 5c is connected to the drain of the transistor Qc and pulled up to a voltage supply Vcc through a resistor R1 (usually several hundreds of kilo-ohms to several mega-ohms). Therefore, when the read voltage is applied to the gate of the transistor Qc stored with information, a read current flows from the voltage supply Vcc into the transistor Qc in accordance with the read voltage. In response, a voltage drop occurring in the resistor R1 in accordance with the above current is detected by the sense amplifier SA as the readout signal. The sense amplifier SA produces the inverted or noninverted voltage in accordance with the voltage of the readout signal. Thus, the binary signal is output from the IC.
On the other hand, in the floating gate type transistor, the on/off threshold voltage of the transistor is determined by how much charge of electrons or holes is accumulated in the floating gate. If the readout voltage is higher than the threshold voltage, the transistor is turned on. If the readout voltage is lower than the threshold voltage, the transistor is turned off. Therefore, the output state corresponding to the regular value stored in the memory cell 1c can be determined for the read voltage applied to the gate of the transistor Qc; that is, the storage state of the memory cell 1c can be detected.
To test the degree of storage state of the selected memory cell 1c, that is, the trap degree of electrons or holes in the floating gate of the transistor Qc, in the test operation the external voltage E, which provides a stricter condition than the standard read voltage S (usually, the former is lower than the latter), is applied to the memory cell 1c as the read voltage. The degree of storage state of the selected memory cell 1c is detected based on the resulting binary output.
As described above, the margin test for the actual read operation can be performed by reading out the information stored in the memory cell under a condition stricter than the normal condition. This enables supply of selected PROM IC products having stable performance.
However, there exist certain types of memory cells which do not allow proper application of the above margin test. An example is a margin test in which the above-mentioned floating gate type transistor is in a depletion state as a result of trapping of holes or release of electrons in the floating gate. To perform a proper margin test on a memory cell whose transistor is in a depletion state, the externally supplied read voltage E should be a negative voltage (about -4 V if possible). However, the performance test cannot be satisfactory with the externally supplied, negative read voltage of about -4 V, because in the above-mentioned floating gate type transistor memory short-circuiting to the grounding terminal occurs in a path leading from the terminal for the external voltage E to the transistor of the selected memory cell due to a parasitic diode existing in a part of the path.
Therefore, conventionally, there is no satisfactory method of conducting the above-described margin test except for the case where the test is performed on a PROM IC in a wafer state having only a circuit dedicated to the margin test or an invasive test or the like is performed on a PROM IC not to become a final product. At present, the margin test on mass-production PROM IC products is performed with the external voltage E of about 0 V in the lowest voltage case, so that the reliability of PROM ICs is not necessarily sufficient.